1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming self-aligned contact (SAC) structures on semiconductor devices and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuit products, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are formed on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (ON-state) and a high impedance state (OFF-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises a doped source region and a separate doped drain region that are formed in a semiconductor substrate. The source and drain regions are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure of the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
Typically, due to the large number of circuit elements, e.g., transistors, and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements, i.e., the transistors, with the metallization layers, an appropriate vertical contact structure to the transistor device is formed, wherein a first end of the vertical contact structure is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the metallization layer by a conductive via. As device dimensions have decreased, and packing densities have increased, the physical space between adjacent gate structures is so small that it is very difficult to accurately position, align and form a contact opening in a layer of insulating material using traditional masking and etching techniques. Accordingly, contact-formation technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structures, the gate cap layer and the sidewall spacers of adjacent gate structures are effectively used as etch masks for selectively removing the silicon dioxide material in order to expose the source/drain regions of the transistors, thereby providing self-aligned trenches which are substantially laterally defined by the spacer structures positioned adjacent the gate structures.
However, the aforementioned process of forming self-aligned contacts results in an undesirable loss of the materials that protect the conductive gate electrode, i.e., the gate cap layer and the sidewall spacers, as will be explained with reference to FIGS. 1A-1B. FIG. 1A schematically illustrates a cross-sectional view of an integrated circuit product 10 at an advanced manufacturing stage. As illustrated, the product 10 comprises a plurality of illustrative gate structures 11 that are formed above a substrate 12, such as a silicon substrate. The gate structures 11 are comprised of an illustrative gate insulation layer 13 and an illustrative gate electrode 14 that are formed in a gate cavity 22 using a gate-last processing technique, an illustrative gate cap layer 16 and sidewall spacers 18. The gate cap layer 16 and sidewall spacers 18 encapsulate and protect the gate electrode 14 and gate insulation layer 13. The gate cap layer 16 and sidewall spacers 18 are typically made of silicon nitride. Also depicted in FIG. 1A are a plurality of raised source/drain regions 20 and a layer of insulating material 23, e.g., silicon dioxide.
FIG. 1B depicts the product 10 after a contact etching process was performed to form a contact opening 24 in the layer of insulating material 23 for a self-aligned contact. Although the contact etch process performed to form the opening 24 is primarily directed at removing the desired portions of the layer of insulating material 23, portions of the protective gate cap layer 16 and the protective sidewall spacers 18 get consumed during the contact etch process, as simplistically depicted in the dashed-line regions 26. Typically, when the layer of insulating material 23 is made of silicon dioxide, and the spacers 18 and gate cap layer 16 are made of silicon nitride, the contact etching process may be a dry, anisotropic (directional) plasma etching process that is intended to selectively remove the silicon dioxide layer 23 relative to the silicon nitride spacers 18/gate cap layer 16 of the gate structure 11. As device dimensions continue to shrink, the process margin for such a dry etching process is reduced, since the cap layer 16 and spacers 18 on advanced generation devices may only be about 25 nm and 7 nm thick, or less, respectively. For example, if only 3 nm of thickness (or width) of the spacers 18 is lost during the contact etching process, then the resulting device 10 may not be acceptable in that many device specifications specify that, after the contact etching process is performed, the final spacer must have a minimum thickness or width of 5 nm.
One possible solution would to employ a wet, isotropic etching process, such as BHF-based process or the well-known Frontier isotropic oxide removal process, to form the contact openings 24. Such wet, isotropic etching processes are desirable because they exhibit a higher degree of etch selectivity (silicon dioxide versus silicon nitride) than does the aforementioned dry anisotropic etching process. Accordingly, less of the spacer 18 and the gate cap layer 16 would be consumed using such a wet etching process. However, given the isotropic (non-directional) nature of such an isotropic etching process, controlling the area or amount of the layer of insulating material 23 that is removed so as to define the contact opening 24, i.e., controlling the size and configuration of the contact opening 24 when viewed from above, is difficult. Absent the ability to control the size and configuration of the contact opening 24, sometimes referred to as “blowing-up the contact opening CD” in the industry, conductive contact structures may be formed in areas where they are not supposed to be and thereby result in the formation of undesirable electrical short-circuits. As one example, absent proper control of the size and shape of the contact opening 24, the conductive contact structure that will ultimately be formed therein may short to adjacent active regions or form around an end of the gate structure, creating a short circuit between the source region and the drain region of one of the transistor devices.
The present disclosure is directed to various methods of forming self-aligned contact (SAC) structures on semiconductor devices and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.